HDPython_core = """
-- XGEN: Autogenerated File

library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


package HDPython_core is 
    procedure push_01(signal clk : in std_logic; self : inout std_logic ; signal data : out std_logic) ;
    procedure pull_01(signal clk : in std_logic; self : inout std_logic ; signal data : in std_logic) ;
    procedure push_01(signal clk : in std_logic; self : inout std_logic_vector ; signal data : out std_logic_vector) ;
    procedure pull_01(signal clk : in std_logic; self : inout std_logic_vector ; signal data  : in std_logic_vector) ;

    procedure push_11(signal clk : in std_logic; signal self : inout std_logic ; signal data : out std_logic) ;
    procedure pull_11(signal clk : in std_logic; signal self : inout std_logic ; signal data : in std_logic) ;
    procedure push_11(signal clk : in std_logic; signal self : inout std_logic_vector ; signal data : out std_logic_vector) ;
    procedure pull_11(signal clk : in std_logic; signal self : inout std_logic_vector ; signal data  : in std_logic_vector) ;


    function ah_min(lhs : integer; rhs : integer) return integer;

    function std_logic_vector_ctr(data : integer; bitwidth : integer) return std_logic_vector;
    function to_bool(data : std_logic_vector) return boolean;

    function std_logic_ctr(data : integer; bitwidth : integer := 1 ) return std_logic;
    function to_bool(data : std_logic) return boolean;

    function unsigned_ctr(data : integer; bitwidth : integer) return unsigned;
    function to_bool(data :  unsigned) return boolean;

    function   signed_ctr(data : integer; bitwidth : integer) return   signed;
    function to_bool(data :  signed) return boolean;

    function   integer_ctr(data : integer; bitwidth : integer) return   integer;
    function to_bool(data :  integer) return boolean;

    function to_bool(data :  boolean) return boolean;
    
end HDPython_core;


package body HDPython_core is
    procedure push_01(signal clk: in std_logic; self : inout std_logic ; signal data : out std_logic) is 
    begin 
        data <= self ;
    end procedure;

    procedure pull_01(signal clk: in std_logic; self : inout std_logic ; signal data : in std_logic) is 
    begin 
        self := data;
    end procedure;

    procedure push_01(signal clk: in std_logic; self : inout std_logic_vector ; signal data : out std_logic_vector) is 
    begin 
        data <= self ;
    end procedure;

    procedure pull_01(signal clk: in std_logic; self : inout std_logic_vector ; signal data  : in std_logic_vector) is 
    begin 
        self := data;
    end procedure;
    
    



    procedure push_11(signal clk: in std_logic; signal self : inout std_logic ; signal data : out std_logic) is 
    begin 
        data <= self ;
    end procedure;

    procedure pull_11(signal clk: in std_logic; signal self : inout std_logic ; signal data : in std_logic) is 
    begin 
        self <= data;
    end procedure;

    procedure push_11(signal clk: in std_logic; signal self : inout std_logic_vector ; signal data : out std_logic_vector) is 
    begin 
        data <= self ;
    end procedure;

    procedure pull_11(signal clk: in std_logic; signal self : inout std_logic_vector ; signal data  : in std_logic_vector) is 
    begin 
        self <= data;
    end procedure;
    
    function ah_min(lhs : integer; rhs : integer) return integer is

    begin 

        if (lhs < rhs) then 
            return lhs;
        end if;

        return rhs;

    end function;

    function std_logic_vector_ctr(data : integer; bitwidth : integer) return std_logic_vector is
        variable ret : std_logic_vector(bitwidth - 1 downto 0) :=( others => '0');
    begin 
        ret := std_logic_vector(to_unsigned(data, ret'length));
        return ret;
    end function;

    function to_bool(data : std_logic_vector) return boolean is 
    begin
        return  (data /= 0);
    end function;

    
    function std_logic_ctr(data : integer; bitwidth : integer := 1 ) return std_logic is 
        variable ret : std_logic := '0';
    begin
        if data > 0 then
            ret := '1';
        end if;
        return ret;
    end function;
    
    function to_bool(data : std_logic) return boolean is 
    begin
        return  data = '1';
    end function;

    function unsigned_ctr(data : integer; bitwidth : integer) return unsigned is 
        variable ret : unsigned(bitwidth - 1 downto 0) :=( others => '0');
    begin
        ret := to_unsigned(data, ret'length);
        return ret;
    end function;

    function to_bool(data :  unsigned) return boolean is 
    begin
        return (data /= 0);
    end function;

    function   signed_ctr(data : integer; bitwidth : integer) return   signed is
        variable ret : signed(bitwidth - 1 downto 0) :=( others => '0');
    begin
        ret :=  to_signed(data, ret'length);
        return ret;
    end function;

    function to_bool(data :  signed) return boolean is 
    begin
        return data /= 0;
    end function;

    function   integer_ctr(data : integer; bitwidth : integer) return   integer is 
        variable ret :integer := 0;
    begin 
        ret :=  data;
        return ret;
    end function;

    function to_bool(data :  integer) return boolean is 
    begin 
        return data /= 0;
    end function;

      function to_bool(data :  boolean) return boolean is 
      begin 
        return data;
      end function;
end HDPython_core;
"""

def generate_files_in_folder(FolderName):
    with open(FolderName+"/HDPython_core.vhd","w",newline="") as f:
        f.write(HDPython_core)

    ## add more files here if needed