## `glbl_lib.clk_gate` (`glbl_lib.clk_gate.ClkGateMod`)

### Parameters

-

### Ports

| Name        | Type      |
| ----        | ----      |
| clk_i (IN)  | ClkType() |
| clk_o (OUT) | ClkType() |
| ena_i (IN)  | EnaType() |

### Submodules

-


## `uart_lib.uart` (`uart_lib.uart.UartMod`)

### Parameters

-

### Ports

| Name                 | Type                 |
| ----                 | ----                 |
| main_i (IN)          | ClkRstAnType()       |
|   main_clk_i (IN)    |   ClkType()          |
|   main_rst_an_i (IN) |   RstAnType()        |
| uart_i (IN)          | UartIoType()         |
|   uart_rx_o (OUT)    |   BitType()          |
|   uart_tx_i (IN)     |   BitType()          |
| bus_i (IN)           | BusType()            |
|   bus_trans_i (IN)   |   TransType()        |
|   bus_addr_i (IN)    |   AddrType(32)       |
|   bus_write_i (IN)   |   WriteType()        |
|   bus_wdata_i (IN)   |   DataType(32)       |
|   bus_ready_o (OUT)  |   BitType(default=1) |
|   bus_resp_o (OUT)   |   RespType()         |
|   bus_rdata_o (OUT)  |   DataType(32)       |

### Submodules

| Name         | Module               |
| ----         | ------               |
| `u_clk_gate` | `glbl_lib.clk_gate`  |
| `u_regf`     | `uart_lib.uart_regf` |
| `u_core`     | `uart_lib.uart_core` |
