Metadata-Version: 2.1
Name: fsva
Version: 0.0.1
Summary: fsva (FuseSoc Verification Automation)
Home-page: https://github.com/m-kru/fsva
Author: Michał Kruszewski
Author-email: mkru@protonmail.com
License: MIT
Description: # fsva - FuseSoc Verification Automation
        
        ## Introduction
        
        FuseSoc Verification Automation (fsva) is a tool that aims to automate the verification process of libraries and HDL design projects managed with [FuseSoc](https://github.com/olofk/fusesoc) build tool/system.
        
        fsva in no way duplicates or replaces functionalities provided by the FuseSoc.
        Colloquially speaking, fsva is a wrapper for FuseSoc, automating the verification process.
        
        ### Why?
        The major goal is to easy integrate project/libraries described in FuseSoc into Continuous Integration workflow.
        FuseSoc is more than good for building and running single targets, however if you want to run multiple verificaiton targets it keeps rebuilding verification frameworks.
        This particular operation is redundant and time consuming.
        fsva assumes that verification frameworks (such as [UVVM](https://github.com/UVVM/UVVM) or [OSVVM](https://github.com/OSVVM/OSVVM)) are already pre-compiled (pre-analyzed) for simulation engines.
        What is more, fsva extends FuseSoc by parsing verification results.
        
        ## How it works
        fsva scans recursively for `.core` files and fetches all targets starting with `tb_` or ending with `_tb`.
        Then it runs these targets calling FuseSoc run command and captures stdout and stderr.
        All verification results, as well as verification summary, are saved as separate files in a directory, which name reflects the UTC time of a verification process startup.
        
        If any extra parsing of the verification results is needed (for example in case of metric driven verification) in the future, it will be based on prefix or suffix indicating verification framework/infrastructure.
        For instance, for UVVM it will be `tb_uvvm_` / `_uvvm_tb`, respectively for OSVVM it will be `tb_osvvm_` / `_osvvm_tb`.
        
        If FuseSoc supports formal verification targets in the future, they will be fetched based on `fv_` prefix or `_fv` suffix.
        
        ## Installation
        Latest stable version of fsva can be installed from [PyPI](https://pypi.org/project/fsva/):
        `pip install --user fsva`.
        
        ## Usage
        
        ### Example
        <p align="center"><img src="/img/demo.gif?raw=true"/></p>
        
        You can also run all testbench targets for single core:
        `fsva core_name`
        or run specific verification target for specific core
        `fsva core_name target_name`.
        When verifying single core or target, the output is printed on the console.
        
        ## Note!
        If you use it with UVVM you need to fix status that is returned when UVVM test bench fails: [Integrating UVVM with Continuous Integration - problem with simulators exit status](https://github.com/UVVM/UVVM/issues/82).
        
        MIT License
        
        Copyright (c) 2019 Michał Kruszewski
        
        Permission is hereby granted, free of charge, to any person obtaining a copy
        of this software and associated documentation files (the "Software"), to deal
        in the Software without restriction, including without limitation the rights
        to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
        copies of the Software, and to permit persons to whom the Software is
        furnished to do so, subject to the following conditions:
        
        The above copyright notice and this permission notice shall be included in all
        copies or substantial portions of the Software.
        
        THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
        IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
        FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
        AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
        LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
        OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
        SOFTWARE.
        
Keywords: verification,simulation,testbench,FuseSoc,VHDL,SystemVerilog,UVVM,OSVVM,GHDL,Questa,HDL,RTL,FPGA
Platform: UNKNOWN
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Topic :: Software Development :: Testing
Classifier: Topic :: Software Development :: Quality Assurance
Classifier: Topic :: Utilities
Classifier: Intended Audience :: End Users/Desktop
Classifier: License :: OSI Approved :: MIT License
Description-Content-Type: text/markdown
